Integrated Circuit Design of The Decoder 6 x 64

07/16/2010 00:00:00

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A decoder is an electronic circuit which is able to convert binary information from n input streams into a maximum of 2n different output streams. It is used in a memory system mainly for addressing purpose. It is also used in binary adders and multipliers which comprise the basic components of more complex systems such as processors. This research aimed to design an integrated circuit decoder 6x64 with small time delay and physical size. The design steps included designing the integrated circuit, logic gates, schematic and layout diagram. The software used in the design and the consecutive analysis was Electric. The layout design was made according to MOSIS design rule for 0,5?m technology. Simulation results showed that the 6x64 decoder could perform satisfactorily. The 1st alternative of the 6x64 decoder which consists of 9 pieces of 3x8 decoders is approximately 0,1mm2 in size and has an average delay of 829 ps. The 2nd alternative of the 6x64 decoder which consists of 1 piece of 2x4 decoder and 4 pieces of 4x16 decoder is approximately 0,07mm2 in size and has an average delay of 888 ps.

Keywords: decoder design, integrated circuit design, Electric, 6x64 decoder