Designing of RISC Processor Interface with Advanced Microcontroller Bus Architecture (AMBA) Based UART by Applying to ModelSim

Writer/Researcher : Catherine Olivia Sereati

Area of Research : Elektronika

Journal : Jurnal Elektro

Volume : 2, No. 2

Year : 2009

Nowadays, RISC (Reduced Instruction Set Computer) architecture processor is incresiangly used in multimedia, telecommunication, and household application. In order to support those application, RISC processor have to be integrated as system-on-chip (SoC) with some peripherals. This level of design requires bus systems which have high performance and low power consumption. In order to solve that problem, AMBA (Advanced Microcontroller Bus Architecture) is used to support interface system between processor and another component or peripheral in SoC level design. The objective of this research is to design an interfacing system based on AMBA and to design peripherals which support RISC Processor. Proposed design used SIEGE32 processor which is based on RISC Architecture which is integrated with UART (Universal Asynchronous Receiver Transmitter) as peripheral for this processor. This system is design and simulated using ModelSim, The simulation result show that this system is work at 180MHz and enable to operate in single transfer mode, where one cycle of AHB or APB could only acces one data packet of one address.

Keywords: RISC, AMBA, UART, SIEGE3