In synthesizing DSP architectures, it is important to minimize the silicon area of the integrated circuits, which is achieved by reducing the number of functional units (adders and multipliers), registers, multiplexers, and interconnecting wires. The Folding transformation is used to systematically determine control circuit in DSP architectures where multiple algorithm are time-multiplex to a single functional units. By executing multiple algorithm operations on a single functional unit, the number of functional units in the system can be reduced, resulting in an integrated circuit with low silicon area. Folding transform reduces critical path, which is increases speed. It also reduces combinational area, but increases delay element area.
Keywords: Folding, infinite impulse response (IIR), digital signal processing