Simulation of VHDL- Based Reed Solomon (15,9) Encoding System

Writer/Researcher : Harlianto Tanudjaja, Hyronima W.B

Area of Research : Signal Processing

Journal : Elektra

Volume : 3, No. 1

Year : 2006

The transmission of information is regarded successful if the received information matches the sent information. However, transmission processes are often disrupted hence the information is affected and results in errors. This research proposes the use of Reed Solomon method to encode the information so that errors can be minimized. The use of Very High Speed Integrated Circuit Hardware Description Language (VHDL) as the programming language is advantageous in that it can describe the digital electronics hardware used. The results of the tests done using digital circuitry simulation program show that Reed Solomon (15,9) encoding system can be used to correct up to 3 symbols, both consecutive and spaced.